library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;

-------------------------------------------------------------------------------
entity r_dominant_latch is
-------------------------------------------------------------------------------
port( 
      -- Inputs: --
      R     : in  std_logic; -- active high
      S     : in  std_logic; -- active high

      -- Outputs: --
      Q     : out std_logic;
      QN    : out std_logic  -- this output is valid only for Mutually exclusive R,S
);           
-------------------------------------------------------------------------------
end r_dominant_latch ;
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
architecture r_dominant_latch_arch of r_dominant_latch is
-------------------------------------------------------------------------------

COMPONENT nr02d2 -- drive x2
PORT(
  a1 : IN std_logic; 
  a2 : IN std_logic;
  zn : OUT std_logic
);
END COMPONENT;
 
 signal q_int, qn_int : std_logic;
 
begin

u_nor_r: nr02d2
port map(
      a1 => R,
      a2 => qn_int,
      zn => q_int
);

u_nor_s: nr02d2
port map(
      a1 => S,
      a2 => q_int,
      zn => qn_int
);

Q  <= q_int;
QN <= qn_int;

-------------------------------------------------------------------------------
end r_dominant_latch_arch;
-------------------------------------------------------------------------------                 

   
-------------------------------------------------------------------------------
configuration  r_dominant_latch_cfg  of r_dominant_latch is
-------------------------------------------------------------------------------
   for r_dominant_latch_arch
   end for;
-------------------------------------------------------------------------------
end  r_dominant_latch_cfg;              
-------------------------------------------------------------------------------
                 
